1. Field of the Invention
The present invention relates to a method of forming semiconductor device, and more particularly relates to a method of forming a capacitor with high capacitance and low voltage coefficient.
2. Description of the Prior Art
As is well known, the capacitance of a parallel plate capacitor is normally a function only of the area of the electrodes, the dielectric constant of the dielectric and the thickness of the dielectric. This assumes that both electrodes are metallic conductors. When one of the electrodes is a semiconductor and is formed at the semiconductor-dielectric interface, even in the absence of any externally applied voltage bias, the capacitance of such a structure is somewhat lower than both metallic electrodes. When voltage is applied across the above described device""s plates, the depletion layer in the semiconductor grows or shrinks, depending on the polarity, thereby reducing or increasing the measured capacitance. In other words, such a device has a high voltage coefficient, in some cases as high as 120 ppm/volt. This is not a problem in many integrated circuits, but this cannot be tolerated in many analog circuits (such as analog to digital converters, for example).
During the manufacture of integrated circuits where capacitors must be included, it has been common practiced to form capacitors in integrated circuits by sandwiching a layer of the silicon oxide known as IPO (or inter-poly oxide) between two layers of polysilicon. In earlier processes such as the standard 0.5 micron mixed-mode process, the two polysilicon layers used for the capacitors were sufficiently heavily doped so that they were electrically degenerate (that is, they exhibited metallic conductivity) and any depletion layer formed at the silicon-dielectric interface would be negligibly thin. More recently, with the development of the 0.35 micron process, changes in processing parameters make the polysilicon layers less heavily doped.
A number of prior art references describe capacitors for incorporation within integrated circuits but most do not address the voltage coefficient issue. Boerstler et al. (U.S. Pat. No. 5,389,832, February 1995) describe capacitors formed from forward biased diodes. Sundaresan (U.S. Pat. No. 5,016,070, May 1991) describes a stacked CMOS SRAM with cross-coupled capacitors. Sato (U.S. Pat. No. 5,211,111, May 1996) teaches use of a trench-stacked capacitor. Himes et al. (U.S. Pat. No. 4,731,696, March 1988) address the voltage coefficient issue and disclose a three plate capacitor structure wherein two layers of dielectric are sandwiched between three conductive plates, the center plate being the semiconductor. Voltage is applied between the center plate and the two outer plates (which are connected to each other).
While this structure should exhibit low voltage coefficient, it requires three separate deposition steps for the electrodes and two separately deposited dielectric layers. The latter limitation can lead to serious problems in the absence of precise thickness and process control during deposition of the two dielectric layers. It also means that the standard manufacturing process will have to be modified if this structure is to be made part of an integrated circuit.
It is an object of the invention to provide a method of forming a capacitor in an integrated circuit. Lightly doping implemented on the top surface of a bottom electrode can improve the capacitance of the capacitor.
It is another object of the invention to provide a method of forming a plate capacitor. Heavily doping implemented in the center region of a bottom electrode can reduce the voltage coefficient of the plate capacitor.
The present invention provides a method of forming a capacitor in an integrated circuit. The method comprises providing a semiconductor substrate having a conductive layer thereon. The partial conductive layer is removed to form an electrode. A plurality of first dopants are implanted on a surface of the electrode to form a first doped region. Then a plurality of second dopants are implanted into the electrode to form a second doped region below the first doped region. Then the capacitor is formed comprising the electrode. The first doped region and the second region can reduce voltage coefficient as well as increase capacitance of the capacitor.